1. Field of the Invention
The present invention relates in general to an integrated circuit and, more specifically, to an address transition detector (ATD) circuit that can produce a pulse that is time-consistent relative to an incoming address transition, regardless of process, voltage or temperature fluctuations to better control an asynchronous memory access time. The ATD circuit includes an integrator that can be employed as a standalone circuit for use whenever a signal transition is to be delayed.
2. Description of the Related Art
The following descriptions and examples are given as background only.
Most electronic systems require some form of storage. The storage device is used to temporarily or permanently store information used by the electronic system. The storage device or memory can be a mass storage device or hard drive or, alternatively, can be embodied upon silicon or a single monolithic substrate, and such forms are known as semiconductor memory. Popular semiconductor memories include random access memory (RAM), read-only memory (ROM), and various off-shoots of such memories.
To access the array of storage cells within semiconductor memory, an address bus, a data bus, and a control bus are needed. Accessing cells within a semiconductor memory array can occur either synchronously or asynchronously. In a synchronous memory device, data read/write cycles are controlled by a clocking signal. Whereas in an asynchronous memory device, data read/write is controlled by the address bus and the control bus.
In general the access time of an asynchronous memory is defined as the time between an address transition and the corresponding data read at the memory output. To improve the access time in an asynchronous memory the input address transitions are used to create an internal pulse that controls various circuits in order to obtain the output data faster. The circuit responsible for generating this pulse is generally known as an address transition detector (ATD) circuit.
In the following descriptions HI refers to a voltage level close or equal to the voltage on the power supply node (VDD), LO refers to a voltage level close or equal to the voltage on the ground supply node (VSS), Vtn refers to the gate transition voltage of a NMOS transistor and Vtp refers to the gate transition voltage of a PMOS transistor. Oftentimes, Vtn and Vtp refer to a threshold voltage in which the corresponding NMOS and PMOS transistors turn on. The term “turn on” refers to a MOS transistors forming a low source-to-drain resistance relative to a high source-to-drain resistance when the transistor is turned off.
An example of an ATD circuit is shown in FIG. 1, with the waveforms shown in FIG. 2. The ATD circuit of FIG. 1 comprises two ATD integrators 102 and 103, their output signal being combined into an output logic gate 106. The first ATD integrator 102 is driven by the address signal (addr) while the second ATD integrator 103 is driven by the complementary addr signal through the inverter 100. In the following description the delays introduced by the gates 100 and 106, and the ATD integrators 102 and 103 when switching in the pre charge state are not shown for sake of brevity in the drawings.
During the initial time frame 107 the ATD integrator 102 is in pre charge state while the ATD integrator 103 is in stand by. When the addr signal falling edge occurs at the time point 108 the ATD integrator 103 transitions into the pre charge state and its output 105n switches immediately from LO to HI, or from a first logic value to a second logic value opposite the first. The ATD integrator 102 goes in standby mode after a period of time td1, at the time point 109, when its output 104n switches from HI to LO. The logic gate 106 provides the ATD pulse between the time points 108 and 109 since both signals 104n and 105n are HI during this timeframe. In a similar way another ATD pulse is generated at the time point 110 for the rising edge of the addr signal.
An example of an ATD integrator in schematic form is shown in FIG. 3, and the waveforms over time on some significant nodes of this circuit are presented in FIG. 4. The waveforms names in FIG. 4 match the corresponding node names in FIG. 3. Referring to FIGS. 3 and 4, the ATD integrator may contain a signal input (in1), a signal output (out1), a control input (m1), two capacitors 19 and 23, a resistor 10, an inverter 8, a pre charge transistor 11, a capacitor switch 14 and an output gate 26.
The capacitor switch may include an inverter 12, and a pass gate 15 and 16. When the control input ml is LO the capacitor 23 is disconnected from the node 20n. When ml is HI, the pass gate is turned on (or “activated”) and the capacitor 23 is connected to the node 20n in parallel to the capacitor 19.
The resistor 10 and the capacitors 19 and 23 form a simple RC integrator. For example, if the control input is LO, then the capacitor 23 is disconnected from the node 20n. Before the expected transition occurs at timeframe 27 the signal at the input in1 is HI, the node 9n is LO, the transistor 11 is turned on thereby pre charging the capacitor 19 at zero voltage (VSS). The output gate 26 has the transistor 25 turned on and the transistor 24 is turned off, therefore the output signal at node out1 is HI.
When the input signal transitions to LO (timeframe 32) the node 9n switches to HI and the transistor 11 turns off, enabling the capacitor 19 to be slowly charged through the resistor 10 until the voltage on node 20n reaches approximately the VDD level. The timeframe between 28 and 31 is also called “the integration time of the RC integrator”.
At the time point 29 the transistor 24 begins to turn ON pulling the output out1 towards zero voltage. The input signal transition is transferred at the output out1 after it is delayed by the amount of time between the time points 32 and 33 as shown in FIG. 4.
Unfortunately, during the time period between 29 and 30, the voltage on node 20n is bigger than Vtn and smaller than VDD-Vtp, therefore both transistors 24 and 25 of the output gate 26 are on, or activated, allowing a large amount of current to flow between the power supply (VDD) and ground (VSS). If this timeframe is very large then a significant amount of energy from the power supply is wasted. Another disadvantage of this circuit is that the output transition may be very slow.
FIGS. 5 and 6 refer to a simplified block diagram of a section of the data read path that can be usually found in asynchronous memories. The address signal passing through the address input buffer 120 can split into two parallel paths: (i) the address path (via address decoders 123, wordline drivers 125) that enables the memory cell 130, and (ii) the ATD pulse path (via ATD block 122, buffers and control circuits 124). The ATD pulse is used to control the bit line equalizers 129 and the sense amplifiers 128. The signal transition 140 at the address pin is delayed by the amount of time Tdel 1 through the circuitry of the address path and enables the memory cell 130 at the time point 141. The signal transition 140 also triggers an ATD pulse that is delayed through the ATD pulse path by the amount of time Tdel 2. To ensure the correct functionality of the asynchronous memory read cycle the memory cell enable signal at node 127 must occur within the ATD pulse at node 126n. This important feature is pictured in FIG. 6 that shows the rising edge 141 occurring within the ATD pulse between time points 142 and 143.
It is very difficult to meet this requirement using conventional ATD integrators within an ATD circuit like those described in FIGS. 1-6 since any change in temperature, voltages of operation or fabrication process such as different doping concentrations, etch chemistry, etc., may affect differently the propagation time through the address path and ATD pulse path. Moreover, the ATD integrator uses a transition delay circuit that produces a delayed transition having an excessive transition time and which consumes too much power during the integration, or transition, time.
It would be desirable to implement an ATD integrator for use in the semiconductor memories, having an output gate with low power consumption during the integration time, a fast output transition at the end of the integration time, and also able to compensate the delay variations over process, voltage and temperature (PVT). The present invention provides a solution to these and other problems, and offers further advantages over conventional ATD integrator and methods of operating the same.